Jake Karrfalt Best Student Paper Award Recipients:

  • 2016: Muralidharan Venkatasubramanian (Auburn University), “Failures Guide Probabilistic Search for a Hard-to-Find Test
  • 2015: Yi Sun (Southern Methodist University), “Using an FPGA in a 3D Stacked IC to Prevent LSIB Bitstream Snooping”
  • 2014: Kai Hu (Duke University), “Testing of Flow-Based Microfluidic Biochips and Experimental Demonstration
  • 2013: Ujjwal Guin (University of Connecticut ), “On Selection of Counterfeit IC Detection Methods“, (co-author: Mohammad Tehranipoor)
  • 2012: Kemal Kulovic (Univ. of Massachusetts – Lowell), “Flexible VITAL Embedded Instruments for Built-In Test of AMS Power SOCs
  • 2011: Marco Donato (Brown Univ.), “Noise-Immune CMOS Circuits for Sub-Threshold Operation Using Schmitt-Trigger Logic” (co-authors: K. Nepal, R. I. Bahar, W. Patterson, A. Zaslavsky, and J. Mundy)
  • 2010: Zahra Lak (McMaster Univ.), “A New Algorithm for Post-Silicon Clock Measurement and Tuning” (co-author: N. Nicolici)
  • 2009: Ke Peng (Univ. of Connecticut), “Efficient Pattern Grading for Small Delay Defects in Digital Integrated Circuits” (co-authors: M. Yilamaz, K. Chakrabarty, and M. Tehranipoor)
  • 2008: Xiaoxiao Wang (Univ. of Connecticut), “Path-RO: On-Chip Critical Path Delay Measurement Under Process Variations” (co-authors: M. Tehranipoor and R. Datta)
  • 2007: Alodeep Sanyal (Univ. of Massachusetts), “A Co-evolutionary Algorithm for Dynamic Power Minimization During Scan Testing” (co-authors: A. Sokolov, Y. Malaiya and D. Whitley)
  • 2006: Nitin Yogi (Auburn Univ.), “High-Level Test Generation for Gate-Level Fault Coverage” (co-author: V. Agrawal)
  • 2005: Jack Smith (Univ. of Vermont), “Automated BIST Testing of Delay Faults in FPGA Interconnect” (co-author: T. Xia)
  • 2004: Anuja Sehgal (Duke Univ.), “Cost-Oriented Test Plan Development for Mixed-Signal SOCs with Wrapped Analog Cores” (co-authors: S. Ozev and K. Chakrabarty)
  • 2003: Dan Zhao (SUNY-Buffalo), “A New Distributed Test Control Architecture with Multiple Wireless Test Connectivity and Communication for Gigahertz System-Chips” (co-authors: S. Upadhyaya, and M. Margala)
  • 2002: Lan Rao (Rutgers Univ.), “New Graphical Iddq Signatures Reduce Defect Level and Yield Loss” (co-authors: M. Bushnell and V. Agrawal)


James Monzel Service Award Recipients: 

  • 2016: Eugene Atwood of IBM and Yu Huang of Mentor Graphics
  • 2015: Paul Reuter of Mentor Graphics
  • 2014: Vishwani D. Agrawal of Auburn U
  • 2013:  J.C. Lo of University of Rhode Island
  • 2012: Charles “Chuck” Stroud for 9 years of service, Chuck has served as Program Chair (2 years), Vice Program Chair (2 years), Steering Committee (5 years), Web Page Administrator (7 years), and provided guidance to a new generation of NATW volunteers
  • 2011: Edmond “Ted” S. Cooley for 20 years of service, Ted has served as program and general chairs, as well as many years as the finance chair. In the words of Jacob Abraham of UT-Austin in the early 2000’s when he came to U. of RI’s Kingston conference complex for NATW,  “Ted is the most efficient and reliable registration and finance chair he knew (in all conferences that he has gone to)”


Excellence in Design and Test Engineering Award Recipients:

  • 2016: Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore Manikas, Ping Gui, R. Iris Bahar, Al Crouch, and John Potter, “Using Existing Reconfigurable Logic in 3D Die Stacks for Test”